Generally, semiconductor devices include a plurality of integrated circuits (ICs). The ICs can be useful for many applications including, but not limited to computers and electronic equipment. The ICs typically contain millions of transistors and other circuit elements that can be fabricated on a single semiconductor chip. For device functionality, a complex signal path will typically be routed to connect the circuit elements distributed on the surface of the semiconductor device. Efficient routing of these signals across the IC can become more difficult as the complexity and the number of elements in the ICs is increased. Thus, the formation of multilevel or multilayered interconnect schemes, including dual damascene, has become more desirable due to their efficacy in providing high-speed signal routing patterns between a large number of transistors on a single semiconductor chip.
In fabricating IC wiring with a multilevel interconnect scheme, an electrically insulating material (oftentimes referred to as a dielectric material or low dielectric constant dielectric material, low-k for short), such as SiO2, will normally be patterned to create openings for conductive lines and/or vias using photolithography and reactive ion etching. These openings formed into the dielectric material are typically filled with an electrically conductive material such as Cu or Al to interconnect the active device regions of the ICs and to the printed circuit board. After the filling process, the semiconductor device is generally planarized by chemical-mechanical polishing. Interconnect structures of dual damascene type are highly preferred in the semiconductor industry.
The realization of conventional architectures includes the use of many layers of different patterning and masking materials (typically up to 8 different layers of materials are employed in the prior art) that are formed atop an underlying interconnect level prior to patterning. For example, a nitride hard mask, a silicon oxide hard mask, and a metal hard mask may all be used in patterning the insulating layer and the dielectric barrier of a typical interconnect structure. After forming the masking layers atop the insulating material, a photoresist and an antireflective coating are generally applied to the uppermost surface of the masking layers. The photoresist is patterned by lithography and thereafter a series of etching steps are employed to first transfer the pattern from the photoresist to an underlying ARC and each of the masking layers, and thereafter to the insulating dielectric layer and a dielectric barrier layer. Furthermore, the masking layers have to be removed after patterning. Therefore, the prior art process of patterning a dielectric material is a very inefficient process.
In recent years, conventional insulating materials such as SiO2 are being phased out and replaced with dielectric materials that have a low-dielectric constant (low-k) associated therewith. The term “low-k” denotes a dielectric material that has a dielectric constant of less than 4.3. For example, various PE CVD deposited inorganic dielectrics such as carbon doped organosilicates or SiCOH have been developed and are currently in the mass production of IC products. To further reduce the dielectric constant, nanoscopic pores have to be introduced into these materials to form porous low-k dielectric materials. These porous low-k dielectrics are particularly advantageous for use as an interconnect dielectric because they significantly reduce signal delay and cross-talk in interconnect structures due to their lower dielectric constants.
The patterning of low-k and porous low-k materials requires the above mentioned multilayer masking scheme. Prior art multilayer masking schemes of the type mentioned above are particularly insufficient because: (i) they need many layers of sacrificial materials; (ii) each individual masking layer needs to be removed after patterning; (iii) the various masking layers sometimes increase the effective dielectric constant of the ICs; (iv) the low-k material can be damaged during the plasma processes, and its' dielectric constant is often increased; and (v) they increase integration complexity and manufacturing costs (i.e., a need for separate photoresists and hardmasks and the related expensive deposition and etching tools).
In the prior art, some photo-patternable low-k (PPLK) materials have been proposed, see, for example, U.S. Pat. No. 7,306,853. The integration of a PPLK material in an interconnect structure typically requires the deposition of a dielectric barrier on a substrate. Then, an antireflective (ARC) layer is formed on top of the barrier layer. In some cases, the dielectric barrier can also play the role of an antireflective coating. As such, a separate ARC is not needed in all instances. The PPLK is deposited atop of the stack, and patterned. In some cases, a second PPLK layer is deposited and patterned to form dual damascene interconnect structures. The PPLK layer(s) is/are cured in order to convert it from a resist-like material into a permanent low-k material that remains within the interconnect structure. An etch process is used to open the ARC and the dielectric barrier. A metal liner and an electrically conductor (typically TaN and copper) are deposited and are polished by chemical mechanical polishing.
With such a PPLK integration scheme, the ARC and cap layer are etched after conversion of the PPLK from a resist into a permanent low-k dielectric. The etch selectivity of the permanent low-k dielectric is generally lower than that of the resist-like PPLK prior to conversion. Additionally, no separate mask is used on top of the PPLK material. As a consequence, an upper portion of the PPLK material is etched, and the edges of the PPLK features can be tapered by the plasma etch process. Furthermore, the PPLK material is potentially damaged by the plasma etch process. More details on the standard integration scheme for PPLK can be found in U.S. Patent Application Publication No. 2009/0079075 A1, the entire contents of which are incorporated herein by reference.
In view of the state of the art mentioned hereinabove, there is a continued need for providing interconnects structures which prevent the use of sacrificial layers, while improving etch selectivity and keeping an undamaged interconnect dielectric.